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features ? can be used as either 1 off 512k x 32, 2 off 512k x 16 or 4 off 512k x 8 ? operating voltage: 3.3v + 0.3v ? access time: ? at68166ft (5v tolerant) . 25 ns (preliminary information) . 17 ns (advanced information) ? at68166f . 15 ns (advanced information) ? very low power consumption ? at68166ft (5v tolerant) . active: 540 mw per byte (max) @ 25 ns - 450 mw per byte (max) @ 50ns . standby: 15 mw (typ) ? at68166f . active: 650 mw per byte (max) @ 15 ns - 540 mw per byte (max) @ 25ns . standby: 15 mw (typ) ? military temperature range: -55 to +125 c ? ttl-compatible inputs and outputs ? asynchronous ? die manufactured on atmel 0.25 m radiation hardened process ? no single event latch up below let threshold of 80 mev/mg/cm 2 ? tested up to a total dose of 300 krads (si) according to mil-std-883 method 1019 ? esd better than 4000v for the at68166f ? esd better than 2000v for the at68166ft ? quality grades: escc, qml-q or v ? 950 mils wide mqfpt 68 package ? mass : 8.5 grams description the at68166f/ft is a 16mbit radiation hardened hermetic multi chip module (mcm), made of very low-power cmos asynchronous static ram which can be orga- nized as 1 bank off 512k x 32, 2 banks off 512kx16, or 4 banks off 512kx8. it is built with 4 dies of the at60142f/ft sram keeping all their basic characteristics: power consumption, stand by current, data retention, multiple bit upset (mbu) immunity, etc? this mcm takes full benefit of atmel expertise in hermetic ceramic package assembly. the small size of the at60142f/ft die allows for assembling it in a 68 pins quad flat pack which results into a package footprint compatible with products from other sources. furthermore, all dies being assembled on the same package side makes power dissipation through the pcb much easier and more efficient. this mcm brings the solution to applications where fast computing is as mandatory as low power consumption and higher integration density, saving 75% of the pcb area used when using the individually packaged 4mb sram. the at68166ft is biased at 3.3v and allows for 5v tolerance. it is available in 25 ns and 17 ns specification. the at68166f is biased at 3.3v and is not 5v tolerant. it is available in 15 ns specification. the at68166f/ft will be processed according to the test methods of the latest revi- sion of the mil-prf-38535 or the escc 9000. 7531c?aero?04/06 rad hard 16 megabit sram multi chip module at68166f at68166ft preliminary
2 7531c?aero?04/06 at68166f/ft preliminary block diagram figure 1. at68166f/ft block diagram figure 2. 512k x 8 banks block diagram (at60142f/ft) a[18:0] oe cs1 we1 i/o[15:8] bank1 512k x 8 cs2 we2 i/o[23:16] bank2 512k x 8 cs3 we3 i/o[31:24] bank3 512k x 8 cs0 we0 i/o[7:0] bank0 512k x 8 or i/o2[31:16] or i/o2[15:0] or i/o1[31:16] or i/o1[15:0] or i/o3[7:0] or i/o2[7:0] or i/o1[7:0] or i/o[7:0] a 0 - - - a 10 i/ox 0 i/ox 7 cs x we x oe
3 7531c?aero?04/06 at68166f/ft preliminary pin configuration table 1. at68166f/ft pin assignement figure 3. at68166f/ft pin assignement lead signal lead signal lead signal lead signal 1 i/o0[0] 18 vdd 35 i/o3[7] 52 vdd 2 i/o0[1] 19 a11 36 i/o3[6] 53 a10 3 i/o0[2] 20 a12 37 i/o3[5] 54 a9 4 i/o0[3] 21 a13 38 i/o3[4] 55 a8 5 i/o0[4] 22 a14 39 i/o3[3] 56 a7 6 i/o0[5] 23 a15 40 i/o3[2] 57 a6 7 i/o0[6] 24 a16 41 i/o3[1] 58 we0 8 i/o0[7] 25 cs0 42 i/o3[0] 59 cs3 9gnd26 oe 43 gnd 60 gnd 10 i/o1[0] 27 cs1 44 i/o2[7] 61 cs2 11 i/o1[1] 28 a17 45 i/o2[6] 62 a5 12 i/o1[2] 29 we1 46 i/o2[5] 63 a4 13 i/o1[3] 30 we2 47 i/o2[4] 64 a3 14 i/o1[4] 31 we3 48 i/o2[3] 65 a2 15 i/o1[5] 32 a18 49 i/o2[2] 66 a1 16 i/o1[6] 33 nc 50 i/o2[1] 67 a0 17 i/o1[7] 34 nc 51 i/o2[0] 68 nc i/o0[0] i/o0[1] i/o0[2] i/o0[3] i/o0[4] i/o0[5] i/o0[6] i/o0[7] gnd i/o1[0] i/o1[1] i/o1[2] i/o1[3] i/o1[4] i/o1[5] i/o1[6] i/o1[7] i/o2[0] i/o2[1] i/o2[2] i/o2[3] i/o2[4] i/o2[5] i/o2[6] i/o2[7] gnd i/o3[0] i/o3[1] i/o3[2] i/o3[3] i/o3[4] i/o3[5] i/o3[6] i/o3[7] at68166f/ft (top view) nc a0 a1 a2 a3 a4 a5 cs2 gnd cs3 we0 a6 a7 a8 a9 a10 vdd nc nc a18 we3 we2 we1 a17 cs1 0e cs0 a16 a15 a14 a13 a12 a11 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
4 7531c?aero?04/06 at68166f/ft preliminary pin description table 2. pin names note: 1. the package lid is connected to gnd table 3. truth table (1) name description a0 - a18 address inputs i/o0 - i/o31 data input/output cs0 - cs3 chip select w e 0 - we3 write enable oe output enable vcc power supply gnd (1) ground cs xw e x oe inputs/outputs mode h x x z standby l h l data out read l l x data in write l h h z output disable note: 1. l=low, h=high, x= h or h, z=high impedance.
5 7531c?aero?04/06 at68166f/ft preliminary electrical characteristics absolute maximum ratings* note: 1. 7v for ft version. 2. for at68166f. it is better than 2000v for at68166ft. military operating range recommended dc operating conditions note: 1. ft version: 5.5v in dc, 5.8v in transient conditions. capacitance note: 1. guaranteed but not tested. supply voltage to gnd potential: ......................... -0.5v + 4.6v dc input voltage:.....................................gnd -0.5v to 4.6v (1) dc output voltage high z state: ................gnd -0.5v to 4.6v storage temperature: ................................... -65 c to + 150 c output current into outputs (low): ............................... 20 ma electro statics discharge voltage (2) :.. .........> 4000v (mil std 883d method 3015.3) *note: stresses beyond those listed under "absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating voltage operating temperature 3.3 + 0.3v -55 c to + 125 c parameter description min typ max unit vcc supply voltage 3 3.3 3.6 v gnd ground 0.0 0.0 0.0 v v il input low voltage gnd - 0.3 0.0 0.8 v v ih input high voltage 2.2 ? v cc + 0.3 (1) v parameter description min typ max unit c in (1) (oe and ax) input capacitance ? ? 48 pf c in (1) (csx and wex) input capacitance ? ? 12 pf c io (1) i/o capacitance ? ? 12 pf
6 7531c?aero?04/06 at68166f/ft preliminary dc parameters notes: 1. gnd < v in < v cc , gnd < v out < v cc output disabled. 2. ft version only: v in = 5.5v, v out = 5.5v, output disabled. 3. v cc min. i ol = 8 ma (f version) - i ol = 6 ma (ft version) 4. 4. v cc min. i oh = -4 ma consumption notes: 1. all csx > v ih 2. all csx > v cc - 0.3v 3. f = 1/ tavav , i out = 0 ma, wex = oe = v ih , v in = gnd/v cc , v cc max. 4. f = 1/ tavaw , i out = 0 ma, we x = v il , oe = v ih , v in = gnd/v cc , v cc max. parameter description minimum typical maximum unit iix (1) input leakage current -1 ? 1 a ioz (1) output leakage current -1 ? 1 a iih (2) at 5.5v input leakage current (oe & axx) -?10 a input leakage current (we & cs ) --5a iozh (2) at 5.5v output leakage current -?5 a vol (3) output low voltage ? ? 0.4 v voh (4) output high voltage 2.4 ? ? v symbol description tavav/tavaw test condition at68166ft-25 (preliminary) at68166ft-17 (advanced) at68166f-15 (advanced) unit value i ccsb (1) standby supply current ?101010mamax i ccsb1 (2) standby supply current ? 8 8 8 ma max i ccop (3) read per byte dynamic operating current 15 ns 17 ns 25 ns 50 ns 1 s - - 150 85 15 - 170 150 85 15 180 - 150 85 15 ma max i ccop (4) write per byte dynamic operating current 15 ns 17 ns 25 ns 50 ns 1 s - - 150 125 110 - 155 150 125 110 160 - 150 125 110 ma max
7 7531c?aero?04/06 at68166f/ft preliminary data retention mode atmel cmos ram's are designed with battery backup in mind. data retention voltage and sup- ply current are guaranteed over temperature. the following rules insure data retention: 1. during data retention chip select csx must be held high within v cc to v cc -0.2v. 2. output enable (oe ) should be held high to keep the ram outputs high impedance, mini- mizing power dissipation. 3. during power-up and power-down transitions csx and oe must be kept between v cc + 0.3v and 70% of v cc . 4. the ram can begin operation > t r ns after v cc reaches the minimum operation voltages (3v). figure 4. data retention timing data retention characteristics vcc csx parameter description min typ t a = 25 cmax unit v ccdr v cc for data retention 2.0 ? ? v t cdr chip deselect to data retention time 0.0 ? ? ns t r operation recovery time t avav (1) 1. t avav = read cycle time. ??ns i ccdr (2) 2. all csx = v cc , v in = gnd/v cc . data retention current ? 3 6 ma
8 7531c?aero?04/06 at68166f/ft preliminary ac characteristics temperature range:................................................ -55 +125 c supply voltage: ....................................................... 3.3 + 0.3v input pulse levels: .................................................. gnd to 3.0v input rise and fall times:....................................... 3ns (10 - 90%) input and output timing reference levels: ............ 1.5v output loading i ol /i oh :............................................ see figure 3 figure 5. ac test loads waveforms write cycle table 4. write cycle timings (2) notes: 1. parameters guaranteed, not tested, with output loading 5 pf. (see ?ac test loads waveforms? on page 8.) 2. timings figures applicable for 8-bit, 16-bit and 32-bit mode. specific (twlqz, twhqx, telqx, tehqz tglqx, tghqz) general symbol parameter at68166ft-25 (preliminary) at68166ft-17 (advanced) at68166f-15 (advanced) unit min max min max min max tavaw write cycle time 20 - 17 - 15 - ns tavwl address set-up time 2 - 0 - 0 - ns tavwh address valid to end of write 14 - 8 - 8 - ns tdvwh data set-up time 9 - 7 - 7 - ns telwh cs low to write end 12 - 12 - 12 - ns twlqz write low to high z (1) -10- 7 - 6 ns twlwh write pulse width 12 - 8 - 8 - ns twhax address hold from end of write 0 - 0 - 0 - ns twhdx data hold time 2 - 0 - 0 - ns twhqx write high to low z (1) 5-3-3- ns
9 7531c?aero?04/06 at68166f/ft preliminary figure 6. write cycle 1. w e controlled, oe high during write figure 7. write cycle 2. w e controlled, oe low figure 8. write cycle 3. cs controlled (1) the internal write time of the memory is defined by the overlap of cs low and we low. both signals must be activated to initiate a write and either signal can terminate a write by going in active mode. the data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. data out is high impedance if oe = v ih . e e address csx wex i/os oe e e address csx wex i/os e address csx wex i/os
10 7531c?aero?04/06 at68166f/ft preliminary read cycle table 5. read cycle timings (2) notes: 1. parameters guaranteed, not tested, with output loading 5 pf. (see ?ac test loads waveforms? on page 8.) 2. timings figures applicable for 8-bit, 16-bit and 32-bit mode. figure 9. read cycle nb 1: address controlled (cs = oe = v il , we = v ih ) figure 10. read cycle nb 2: chip select controlled (we = v ih ) symbol parameter at68166ft-25 (preliminary) at68166ft-17 (advanced) at68166f-15 (advanced) unit min max min max min max tavav read cycle time 25 17 15 ns tavqv address access time 25 17 15 ns tavqx address valid to low z 5 5 5 ns telqv chip-select access time 25 17 15 ns telqx cs low to low z (1) 555ns tehqz cs high to high z (1) 10 7 6 ns tglqv output enable access time 12 8 6 ns tglqx oe low to low z (1) 222ns tghqz oe high to high z (1) 10 6 5 ns address dout csx oe dout
11 7531c?aero?04/06 at68166f/ft preliminary typical applications this section presents some standard implementations of the at68166f/ft in application. 32-bit mode application when used on a 32-bit (word) application, the module shall be connected as follow : ? the 32 lines of data are connected to distinct data lines ? the four csx are connected together and linked to a single host cs output ? each one of the four we x is connected to a dedicated we line on the host to allow byte, half word and word format write. figure 11. 32-bit typical application ( 1 sram bank) 16-bit mode application when used on a 16-bit (half word) application, the module can be connected as presented in the following figure. this allows use of a single at68166f/ft part for two sram memory banks. all input controls of the at68166f/ft not used in the application shall be pulled-up. figure 12. 16-bit typical application (two sram banks) 8-bit mode application when used on a 8-bit (byte) application, the module can be connected as presented in the fol- lowing figure. this allows use of a single at68166f/ft part for up to four sram memory banks. all input controls of the at68166f/ft not used in the application shall be pulled-up. cs [3:0] oe we [3:0] a[17:0] i/o[31:0] at68166f/ft ramoe0* ad at697e a[27:0] d[31:0] d[31:0] a[19:2] rwe[3:0]* rams0* a[19:2] d[31:0] a[17:0] i/o[15:0] at68166f/ft a d at697e a[27:0] d[31:0] d[31:16] a[18:1] a[18:1] d[31:0] i/o[31:16] d[31:16] cs [1:0] we [1:0] rwe0* rams0* cs [3:2] we [3:2] rwe0* rams1* oe ramoe[1:0]*
12 7531c?aero?04/06 at68166f/ft preliminary figure 13. 8-bit typical application (two sram banks) a[17:0] i/o[7:0] at68166f/ft a d at697e a[27:0] d[31:0] d[31:24] a[17:0] a[17:0] d[31:0] i/o[15:8] d[31:24] cs [0] we [0] rwe0* rams0* cs [1] we [1] rwe0* rams1* oe ramoe[1:0]* cs [3] we [3] rwe0* rams2* cs [2] we [2] rwe0* rams2* i/o[23:16] d[31:24] i/o[31:24] d[31:24]
13 7531c?aero?04/06 at68166f/ft preliminary ordering information part number temperature range speed package flow at68166ft at68166ft-ym25-e 25 c 25 ns/5v tol. mqfpt68l engineering samples at68166ft-ym25mq -55 to +125 c 25 ns/5v tol. mqfpt68l qml q at68166ft-ym25sv -55 to +125 c 25 ns/5v tol. mqfpt68l qml v at68166ft-ym25escc -55 to +125 c 25 ns/5v tol. mqfpt68l escc AT68166FT-YM17-E 25 c 17 ns/5v tol. mqfpt68l engineering samples at68166f at68166f-ym15-e 25 c 15 ns/3.3v mqfpt68l engineering samples
14 7531c?aero?04/06 at68166f/ft preliminary package drawings 68-lead quad flat pack (950 mils) with non conductive tie bar note: lid is connected to ground.
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